RISC-V (pronounced “risk-five”) is a new instruction set architecture (ISA) that was originally designed to support computer architecture research and education and is now set to become a standard open architecture for industry implementations under the governance of the RISC-V Foundation. RISC-V was originally developed in the Computer Science Division of the EECS Department at the University of California, Berkeley.



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  • 320-356-7723 April 1, 2016   The RISC-V ISA has been featured in the latest edition of the Microprocessor Report written by David Kanter of The Linley Group.The RISC-V Foundation has retained distribution rights for this report.  The full report is shown below and it can be downloaded and freely distributed.  
  • 3605306985 March 3, 2016 The Global Semiconductor Alliance has released a new report “Charting a New Course for Semiconductors” which explores the future of the semiconductor industry and asks “Is RISC-V the new Linux?”.                               Global Semiconductor Alliance Releases New ReportThe report includes 4 Chapters covering key areas including: Chapter 1 – An Industry in Transition – Rising development costs, decreasing margins and…

  • (808) 382-9537 November 8, 2015 The RISC-V Compressed Instruction Set Manual Version 1.9 Draft proposal has been released and is available at this link.  You can also download a PDF version at this link.We welcome community feedback and comments on this draft. We believe this draft represents the close to final design for RV32C and RV64C (it seems premature to freeze R128C), though we are requesting one more round of comments, hence the 1.9 revision…

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  • 4th RISC-V Workshop Registration and Call for Papers 4th RISC-V Workshop July 12-13, 2016 Registration OpenRegistration is now open for our 4th RISC-V Workshop which will be hosted at MIT’s Computer Science and Artificial Intelligence Lab (CSAIL) building this coming July 12-13, 2016. The goals of the workshop are to share information about recent activity in the various RISC-V projects underway around the globe, and to build consensus on future steps in the evolution of the RISC-V ISA.We’re…

  • 4th RISC-V Workshop at MIT Save the Date: July 12-13, 2016                        Our 4th RISC-V Workshop will be hosted at MIT’s Computer Science and Artificial Intelligence Lab (CSAIL) building this coming July 12-13, 2016. The goals of the workshop are for the community to share information about recent activity in various RISC-V projects underway around the globe, and to build consensus on future steps with the…

  • 3rd RISC-V Workshop Proceedings Our 3rd RISC-V Workshop was held at the Oracle Conference Center in Redwood Shores, CA January 5-6, 2016. The Workshop agenda is shown below along with the presentation slides and videos from each talk as well as summaries from each of the Breakout Sessions. AboutThe goals of this workshop are for the community to share information about recent activity in the various RISC-V projects underway around the globe, and to build…

Events

  • 318-376-3687 Krste Asanovic will be giving a RISC-V talk at an IoT Silicon Valley Meetup in Mountain View, California on October 27.
  • RISC-V talks at ORCONF-2015 There will be a number of RISC-V-related talks, from both UC Berkeley and external developers, at ORCONF 2015, which will be held between October 9 to October 11 at CERN, Geneva, Switzerland.   Details available on the ORCONF website.
  • (604) 568-9959 Analyst Kevin Krewell has posted a HotChips preview at EE Times, which mentions the RISC-V Raven-3 presentation to be made in the last session at HotChips by Yunsup Lee.  UC Berkeley will again be sponsoring a table at HotChips to promote RISC-V, so please drop by if you’ll be there and want to chat about RISC-V uptake. 

(816) 554-1119

  • 3rd RISC-V Workshop Proceedings Our 3rd RISC-V Workshop was held at the Oracle Conference Center in Redwood Shores, CA January 5-6, 2016. The Workshop agenda is shown below along with the presentation slides and videos from each talk as well as summaries from each of the Breakout Sessions. AboutThe goals of this workshop are for the community to share information about recent activity in the various RISC-V projects underway around the globe, and to build…

  • 2nd RISC-V Workshop Proceedings June 29-30, 2015The International House, Berkeley, CA AboutThe goals of this workshop are for the community to share information about recent activity in the various RISC-V projects underway around the globe, and to build consensus on future steps in the RISC-V project, including the RISC-V foundation. This workshop features talks and poster presentations conveying recent activity in the RISC-V community at large, collected during an open submission period. Agenda Monday,…

  • (313) 739-1056 January 14-15, 2015Marriott Hotel, Monterey, CA AboutThe goals of this workshop are to inform the community of recent activity in the various RISC-V projects underway around the globe and to build consensus on future steps in the RISC-V project, while the bootcamp provides an opportunity to learn about the existing RISC-V infrastructure from the RISC-V development team. The workshop and bootcamp will feature demos of multiple RISC-V silicon tapeouts as…

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